The EtherCAT IP core enables the EtherCAT communication function and application-specific functions to be implemented on an FPGA (Field Programmable Gate Array – i.e. a block containing programmable logical components). The EtherCAT functionality is freely configurable.

The IP core can be combined with own FPGA designs and offers the option of communicating with a soft core processor via the OPB (Xilinx) interface. The physical interfaces and internal functions, such as the number of FMMUs and Sync Managers, the size of the DPRAM, etc., are adjustable. The process data interface (PDI) and the distributed clocks are also configurable. The functions are compatible with the EtherCAT specification and the EtherCAT ASICs (ET1100, ET1200).

The number of required logic elements depends on the chosen configuration:

• 32 bit digital I/O, 1 kB RAM without distributed clocks with FMMU and Sync Manager with approx. 2,500 slices (Spartan-3E)
• 16 bit μC interface, 60 kB RAM, with distributed clocks, 8 FMMUs and 8 Sync Managers with approx. 8,000 slices (Spartan-3E)

The EtherCAT Xilinx IP core can be used with the following FPGAs:

• Spartan-3, Spartan-3E, Spartan-3A
• Virtex-II, Virtex-II Pro, Virtex-II Pro X, Virtex-4 and Virtex-5.